This invention relates to lateral metal-oxide-semiconductor field effect transistors (LMOSFETs) used in high-power applications such as UHF transmission which are especially suited for silicon carbide (SiC) technology. In particular, the invention relates to an n-channel SiC power LMOSFET built on a highly-doped n-type SiC substrate, wherein a highly-doped n-type sinker provides a grounding path to the highly-doped n-type substrate, a highly-doped p-type buffer layer is provided to ensure against parasitic NPN transistor losses, and a lightly-doped p-type epitaxial layer provides a channel region for the device.
In recent years, the use of silicon lateral double-diffused metal-oxide-semiconductor field effect transistors (Si LDMOSFETs) in high-power applications such as cellular and UHF broadcast transmission has increased enormously. This is because Si LDMOSFETs offer higher gain and better linearity than bipolar devices.
It is desirable to fabricate these power Si LDMOSFETs with n-channel structures and grounded substrates to reduce parasitic effects. As shown in FIG. 1, this is typically achieved by fabricating a power Si LDMOSFET 10 with a highly doped p-type substrate 12 and a highly doped p-type diffusion or sinker 14 which grounds the substrate 12 in order to desirably reduce parasitic effects.
Silicon carbide (SiC) is an attractive semiconductor material for high frequency and high power applications. The properties which make SiC attractive for high power UHF applications are its large critical electric field (10 times that of Si) and its large electron saturation velocity (2 times that of Si). The large critical electric field helps increase the breakdown voltage of the device and the large saturation velocity helps increase the peak current.
Theoretically, it should be possible to achieve power densities which are 20 times higher than that of Si LDMOSFETs with comparable feature sizes in SiC LDMOSFETs. The operating frequency and gain should be similar for both Si and SiC devices with comparable gate lengths. Hence, it would be desirable to fabricate the LDMOSFET structure shown in FIG. 1 in SiC instead of Si.
Unfortunately, there are many practical difficulties in achieving such an n-channel LDMOSFET structure in SiC. It is not possible to diffuse the dopants in SiC thus only high energy ion implantation can be used to fabricate deep p-type sinkers. However, these p-type implanted SiC layers have very high resistivities. The lowest reported sheet resistance to date for implanted p-type layers is about 10 kxcexa9/sq (all sheet resistance data discussed herein is at 20xc2x0 C.) This data suggests that it will not be possible to form low resistivity highly doped p-type sinkers in SiC.
Another difficulty in achieving the MOSFET structure shown in FIG. 1 in SiC relates to the very high resistivities of SiC p-type substrates. The resistivity of p-type SiC substrates is only about 5 xcexa9/sq. In comparison, p-type Si substrates used in Si LDMOSFETs have resistivities as low as about 0.014 xcexa9/sq.
Still another difficulty in achieving the FIG. 1 MOSFET structure in SiC concerns the formation of the channel of the device. In Si n-channel LDMOSFETs, the channel is formed via an inversion region 18, in an implanted p-type layer 16 (P base) as shown in FIG. 1. This may not be practical to do in SiC devices because the inversion region formed in the implanted surface of a SiC p-type epilayer results in very low inversion layer mobility (less than about 1 cm2/Vs). Inversion layer mobilities higher than about 100 cm2/Vs have only been achieved on epitaxial p-type SiC layers as reported by Alok et al., xe2x80x9cProcess Dependence of Inversion Layer Mobility in 4Hxe2x80x94SiC Devicesxe2x80x9d, at the International Conference on Silicon Carbide and Related Materials in Raleigh, (N.C.) in October 1999.
One possible solution to the substrate grounding problem in n-channel SiC MOSFET devices is to use a p-channel structure in the device with an n-type SiC substrate. The resistivity of n-type SiC substrates and implanted layers is about 2 orders-of-magnitudes lower than that of p-type in SiC. The lowest sheet resistance of implanted n-type SiC layers is about 200 xcexa9/sq and the lowest sheet resistance of n-type SiC substrate is about 0.02 xcexa9/sq. However, p-channel SiC MOSFETs are affected by hole mobilities which are two orders-of-magnitude lower than electron mobilities.
Therefore, an n-channel SiC power lateral MOSFET structure is needed which overcomes the above problems.
A lateral metal-oxide-semiconductor field effect transistor (LMOSFET) comprising a layer of silicon carbide semiconductor material having a p-type conductivity, source and drain regions having n-type conductivities disposed in the silicon carbide semiconductor layer, and an insulated gate electrode disposed on the silicon carbide semiconductor layer. A silicon carbide semiconductor substrate having an n-type conductivity, supports the p-type conductivity silicon carbide semiconductor layer.
One aspect of the invention involves providing a sinker region having an n-type conductivity, in the silicon carbide p-type semiconductor layer. The sinker region extends from the source contact to the silicon carbide semiconductor substrate to ground the substrate.
Another aspect of the invention involves providing a second layer of silicon carbide semiconductor material having a p-type conductivity, between the substrate and the first silicon carbide semiconductor layer. The second layer of silicon carbide prevents parasitic transistor effects.